Routing-directed Placement for the TRIPTYCH FPGA

Currently, FPGAs either divorce the issues of placement and routing by providing logic and interconnect as separate resources, or ignore the issue of routing by targeting applications that use only nearest-neighbor communication. Triptych is a new FPGA architecture that attempts to support efficient implementation of a wide range of circuits by blending the logic and interconnect resources. This allows the physical structure of the logic array to more closely match the structure of logic functions, thereby providing an efficient substrate (in terms of both area and speed) in which to implement these functions. Full utilization of this architecture requires an integrated approach to the mapping process which consists of covering, placement, and routing. While our primary goal in this work is to develop effective mapping tools for the Triptych architecture, more tightly-coupled placement and routing will be an important approach for both general-purpose and domain-specific FPGAs. In this paper, we demonstrate that a routing-directed placement algorithm for Triptych should lead to cost-effective mappings when compared to other FPGAs.